Visvesh Sathe

Publication Activity (10 Years)

Years Active: 2016-2022
Publications (10 Years): 21

Top Topics

Top Venues

IEEE J. Solid State Circuits

Publications

James D. Rosenthal, Arindam Mandal, Visvesh Sathe, Matthew S. Reynolds
An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS. RFID (2022)
Deniz Dosluoglu, Kun-Da Chu, Diego Peña-Colaiocco, Ivan Zhao, Visvesh Sathe, Jacques C. Rudell
A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver. ESSCIRC (2022)
Sumanth Gudaparthi, Sarabjeet Singh, Surya Narayanan, Rajeev Balasubramonian, Visvesh Sathe
CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration. HPCA (2022)
Chi-Hsiang Huang, Xun Sun, Yidong Chen, Rajesh Pamula, Arindam Mandal, Visvesh Sathe
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS. ISSCC (2021)
John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Eric P. Pepin, Steve I. Perlmutter, Visvesh Sathe, Jacques Christophe Rudell
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS. IEEE J. Solid State Circuits 55 (7) (2020)
Yi Shen, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Xin Xin, Shubin Liu, Zhangming Zhu, Visvesh Sathe, Nan Sun
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. IEEE J. Solid State Circuits 55 (3) (2020)
Sung Kim, Visvesh Sathe
Bandwidth Extension on Raw Audio via Generative Adversarial Networks. CoRR (2019)
Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun
A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. CICC (2019)
Fahim ur Rahman, Greg Taylor, Visvesh Sathe
A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation. IEEE J. Solid State Circuits 54 (9) (2019)
Fahim ur Rahman, Rajesh Pamula, Akshat Boora, Xun Sun, Visvesh Sathe
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS. ISSCC (2019)
Xun Sun, Akshat Boora, Wenbing Zhang, Venkata Rajesh Pamula, Visvesh Sathe
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS. ISSCC (2019)
John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Steve I. Perlmutter, Visvesh Sathe, Jacques Christophe Rudell
A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS. ESSCIRC (2019)
Fahim U. Rahman, Visvesh Sathe
Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems. IEEE J. Solid State Circuits 53 (3) (2018)
Sung Kim, Patrick Howe, Thierry Moreau, Armin Alaghi, Luis Ceze, Visvesh Sathe
MATIC: Learning around errors for efficient low-voltage neural network accelerators. DATE (2018)
Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze
Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing. DATE (2017)
Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze
Energy-Efficient Hybrid Stochastic-Binary Neural Networks for Near-Sensor Computing. CoRR (2017)
Amrita Mazumdar, Thierry Moreau, Sung Kim, Meghan Cowan, Armin Alaghi, Luis Ceze, Mark Oskin, Visvesh Sathe
Exploring Computation-Communication Tradeoffs in Camera Systems. CoRR (2017)
Amrita Mazumdar, Thierry Moreau, Sung Kim, Meghan Cowan, Armin Alaghi, Luis Ceze, Mark Oskin, Visvesh Sathe
Exploring computation-communication tradeoffs in camera systems. IISWC (2017)
Ali Najafi, Jacques Christophe Rudell, Visvesh Sathe
Regenerative Breaking: Recovering Stored Energy from Inactive Voltage Domains for Energy-efficient Systems-on-Chip. ISLPED (2016)
Samantak Gangopadhyay, Saad Bin Nasir, A. Subramanian, Visvesh Sathe, Arijit Raychowdhury
UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction. ESSCIRC (2016)
Visvesh Sathe, Andrew Marshall
Tutorial 4A: Supply voltage noise and mitigation for real world SoCs. SoCC (2016)