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Rajesh Pamula
ORCID
Publication Activity (10 Years)
Years Active: 2018-2021
Publications (10 Years): 10
Top Topics
Cmos Technology
Metal Oxide Semiconductor
Model Predictive Control
Total Energy
Top Venues
VLSI Circuits
ISSCC
IEEE J. Solid State Circuits
CICC
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Publications
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Arindam Mandal
,
Diego Peña
,
Rajesh Pamula
,
Karam Khateeb
,
Logan Murphy
,
Azadeh Yazdan-Shahmorad
,
Steve I. Perlmutter
,
Forrest Pape
,
Jacques Christophe Rudell
,
Visvesh S. Sathe
A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation.
CICC
(2021)
Chi-Hsiang Huang
,
Xun Sun
,
Yidong Chen
,
Rajesh Pamula
,
Arindam Mandal
,
Visvesh Sathe
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS.
ISSCC
(2021)
Xun Sun
,
Akshat Boora
,
Rajesh Pamula
,
Chi-Hsiang Huang
,
Diego Peña-Colaiocco
,
Visvesh S. Sathe
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS.
VLSI Circuits
(2020)
Fahim ur Rahman
,
Rajesh Pamula
,
Visvesh S. Sathe
Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS.
IEEE J. Solid State Circuits
55 (2) (2020)
Xun Sun
,
Akshat Boora
,
Rajesh Pamula
,
Chi-Hsiang Huang
,
Diego Peña-Colaiocco
,
Visvesh S. Sathe
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS.
VLSI Circuits
(2020)
Fahim ur Rahman
,
Sung Kim
,
Naveen John
,
Roshan Kumar
,
Xi Li
,
Rajesh Pamula
,
Keith A. Bowman
,
Visvesh S. Sathe
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains.
IEEE J. Solid State Circuits
54 (4) (2019)
Fahim ur Rahman
,
Rajesh Pamula
,
Akshat Boora
,
Xun Sun
,
Visvesh Sathe
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS.
ISSCC
(2019)
Fahim ur Rahman
,
Sung Kim
,
Naveen John
,
Roshan Kumar
,
Xi Li
,
Rajesh Pamula
,
Keith A. Bowman
,
Visvesh S. Sathe
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor.
VLSI Circuits
(2018)
Rajesh Pamula
,
Xun Sun
,
Sung Kim
,
Fahim ur Rahman
,
Baosen Zhang
,
Visvesh S. Sathe
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS.
VLSI Circuits
(2018)
Vincent T. Lee
,
Armin Alaghi
,
Rajesh Pamula
,
Visvesh S. Sathe
,
Luis Ceze
,
Mark Oskin
Architecture Considerations for Stochastic Computing Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
37 (11) (2018)