Fahim ur Rahman

Publication Activity (10 Years)

Years Active: 2018-2020
Publications (10 Years): 8

Top Topics

Cmos Technology

Bias Correction

Metal Oxide Semiconductor

Top Venues

IEEE J. Solid State Circuits

Publications

Fahim ur Rahman, Rajesh Pamula, Visvesh S. Sathe
Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS. IEEE J. Solid State Circuits 55 (2) (2020)
Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. IEEE J. Solid State Circuits 54 (4) (2019)
Fahim ur Rahman, Greg Taylor, Visvesh Sathe
A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation. IEEE J. Solid State Circuits 54 (9) (2019)
Fahim ur Rahman, Rajesh Pamula, Akshat Boora, Xun Sun, Visvesh Sathe
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS. ISSCC (2019)
Xun Sun, Fahim ur Rahman, Venkata Rajesh Pamula, Sung Kim, Xi Li, Naveen John, Visvesh S. Sathe
-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor. IEEE J. Solid State Circuits 54 (11) (2019)
Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li, Naveen John, Visvesh S. Sathe
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. ISSCC (2018)
Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. VLSI Circuits (2018)
Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, Visvesh S. Sathe
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. VLSI Circuits (2018)