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-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor.
Xun Sun
Fahim ur Rahman
Venkata Rajesh Pamula
Sung Kim
Xi Li
Naveen John
Visvesh S. Sathe
Published in:
IEEE J. Solid State Circuits (2019)
Keyphrases
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human brain
high speed
information processing
neural network
single chip
learning algorithm
objective function
parallel processing
visual cortex
case study
upper bound
maximum margin
parallel processors
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