Venkata Rajesh Pamula

Publication Activity (10 Years)

Years Active: 2018-2022
Publications (10 Years): 7

Top Topics

Event Related Potentials

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Biomed. Circuits Syst.

Publications

Chi-Hsiang Huang, Yidong Chen, Xun Sun, Arindam Mandal, Venkata Rajesh Pamula, Nasser A. Kurd, Visvesh S. Sathe
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. IEEE J. Solid State Circuits 57 (1) (2022)
John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Eric P. Pepin, Steve I. Perlmutter, Visvesh Sathe, Jacques Christophe Rudell
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS. IEEE J. Solid State Circuits 55 (7) (2020)
John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Steve I. Perlmutter, Jacques Christophe Rudell, Visvesh S. Sathe
/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression. IEEE Trans. Biomed. Circuits Syst. 14 (2) (2020)
Xun Sun, Akshat Boora, Wenbing Zhang, Venkata Rajesh Pamula, Visvesh Sathe
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS. ISSCC (2019)
John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Steve I. Perlmutter, Visvesh Sathe, Jacques Christophe Rudell
A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS. ESSCIRC (2019)
Xun Sun, Fahim ur Rahman, Venkata Rajesh Pamula, Sung Kim, Xi Li, Naveen John, Visvesh S. Sathe
-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor. IEEE J. Solid State Circuits 54 (11) (2019)
Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li, Naveen John, Visvesh S. Sathe
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. ISSCC (2018)