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CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models.
Norman P. Jouppi
Andrew B. Kahng
Naveen Muralimanohar
Vaishnav Srinivas
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2015)
Keyphrases
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high speed
machine learning
low cost
parameter estimation
complex systems
chip design