Jiaxi Zhang

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 32

Top Topics

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Ruiyang Ma, Yuxin Yang, Ziqian Liu, Jiaxi Zhang, Min Li, Junhua Huang, Guojie Luo
VerilogReader: LLM-Aided Hardware Test Generation. CoRR (2024)
Sunan Zou, Jiaxi Zhang, Guojie Luo
Incremental SAT-based Exact Synthesis. ACM Great Lakes Symposium on VLSI (2024)
Sunan Zou, Jiaxi Zhang, Bizhao Shi, Guojie Luo
BESWAC: Boosting Exact Synthesis via Wiser SAT Solver Call. DATE (2024)
Sunan Zou, Jiaxi Zhang, Bizhao Shi, Guojie Luo
PowerSyn: A Logic Synthesis Framework With Early Power Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (1) (2024)
Cong Li, Zhe Zhou, Size Zheng, Jiaxi Zhang, Yun Liang, Guangyu Sun
SpecPIM: Accelerating Speculative Inference on PIM-Enabled System via Architecture-Dataflow Co-Exploration. ASPLOS (3) (2024)
Yonghe Zhang, Liwei Ni, Jiaxi Zhang, Guojie Luo, Huawei Li, Shenggen Zheng
Fast Exact NPN Classification with Influence-Aided Canonical Form. ICCAD (2023)
Jiaxi Zhang, Shenggen Zheng, Liwei Ni, Huawei Li, Guojie Luo
Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions. DATE (2023)
Liwei Ni, Zonglin Yang, Jiaxi Zhang, Changhong Feng, Jianhua Liu, Guojie Luo, Huawei Li, Biwei Xie, Xingquan Li
MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA. CoRR (2023)
Bizhao Shi, Jiaxi Zhang, Zhuolun He, Xuechao Wei, Sicheng Li, Guojie Luo, Hongzhong Zheng, Yuan Xie
Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Jiaxi Zhang, Shenggen Zheng, Liwei Ni, Huawei Li, Guojie Luo
Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions. CoRR (2023)
Yonghe Zhang, Liwei Ni, Jiaxi Zhang, Guojie Luo, Huawei Li, Shenggen Zheng
Fast Exact NPN Classification with Influence-aided Canonical Form. CoRR (2023)
Alberto L. Sangiovanni-Vincentelli, Zheng Liang, Zhe Zhou, Jiaxi Zhang
Automated Design of Chiplets. ISPD (2023)
Tao Yang, Dongyue Li, Fei Ma, Zhuoran Song, Yilong Zhao, Jiaxi Zhang, Fangxin Liu, Li Jiang
PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (1) (2023)
Xinming Wei, Jiaxi Zhang, Guojie Luo
GDSII-Guard: ECO Anti-Trojan Optimization with Exploratory Timing-Security Trade-Offs. DAC (2023)
Liwei Ni, Zonglin Yang, Jiaxi Zhang, Junfeng Liu, Huawei Li, Biwei Xie, Xinquan Li
Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning. CoRR (2023)
Liwei Ni, Zonglin Yang, Jiaxi Zhang, Junfeng Liu, Huawei Li, Biwei Xie, Xinquan Li
Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning. ICCD (2023)
Jiaxi Zhang, Qiuyang Gao, Yijiang Guo, Bizhao Shi, Guojie Luo
EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper). ASP-DAC (2022)
Yijiang Guo, Xinming Wei, Jiaxi Zhang, Guojie Luo
Purlin: A Versatile Toolkit for the Generation and Simulation of On-Chip Networks. ICCD (2022)
Jiaxi Zhang, Liwei Ni, Shenggen Zheng, Hao Liu, Xiangfu Zou, Feng Wang, Guojie Luo
Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning. CoRR (2021)
Jiaxi Zhang, Liwei Ni, Shenggen Zheng, Hao Liu, Xiangfu Zou, Feng Wang, Guojie Luo
Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning. ICCAD (2021)
Jiaxi Zhang, Tao Yang, Qingzheng Li, Bo Zhou, Yang Yang, Guojie Luo, Jianping Shi
An FPGA-Based Neural Network Overlay for ADAS Supporting Multi-Model and Multi-Mode. ISCAS (2021)
Yijiang Guo, Jiarui Wang, Jiaxi Zhang, Guojie Luo
Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping. DAC (2021)
Feng Wang, Guojie Luo, Guangyu Sun, Jiaxi Zhang, Jinfeng Kang, Yuhao Wang, Dimin Niu, Hongzhong Zheng
STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (5) (2021)
Feng Wang, Liren Zhu, Jiaxi Zhang, Lei Li, Yang Zhang, Guojie Luo
Dual-Output LUT Merging during FPGA Technology Mapping. ICCAD (2020)
Wentai Zhang, Jiaxi Zhang, Minghua Shen, Guojie Luo, Nong Xiao
An Efficient Mapping Approach to Large-Scale DNNs on Multi-FPGA Architectures. DATE (2019)
Feng Wang, Guojie Luo, Guangyu Sun, Jiaxi Zhang, Peng Huang, Jinfeng Kang
Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design. ASAP (2019)
Jiaxi Zhang, Wentai Zhang, Guojie Luo, Xuechao Wei, Yun Liang, Jason Cong
Frequency Improvement of Systolic Array-Based CNNs on FPGAs. ISCAS (2019)
Wentai Zhang, Hanxian Huang, Jiaxi Zhang, Ming Jiang, Guojie Luo
Adaptive-precision framework for SGD using deep Q-learning. ICCAD (2018)
Minghua Shen, Jiaxi Zhang, Nong Xiao, Guojie Luo
BoxPlacer: Force Directed-Based Timing-Driven Placement for Large-Scale FPGAs: (Abstract Only). FPGA (2018)
Wentai Zhang, Jiaxi Zhang, Minghua Shen, Nong Xiao, Guojie Luo
Mapping Large-Scale DNNs on Asymmetric FPGAs: (Abstract Only). FPGA (2018)
Feng Wang, Jiaxi Zhang, Lange Wu, Wentai Zhang, Guojie Luo
Search space reduction for the non-exact projective NPNP Boolean matching problem. ISCAS (2017)
Guojie Luo, Wentai Zhang, Jiaxi Zhang, Jason Cong
Scaling Up Physical Design: Challenges and Opportunities. ISPD (2016)