Zhuolun He

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 25

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Publications

Fangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen, Bei Yu
CBTune: Contextual Bandit Tuning for Logic Synthesis. DATE (2024)
Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs. ISPD (2024)
Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu
IncreMacro: Incremental Macro Placement Refinement. ISPD (2024)
Haisheng Zheng, Zhuolun He, Fangzhou Liu, Zehua Pei, Bei Yu
LSTP: A Logic Synthesis Timing Predictor. ASPDAC (2024)
Yuan Pu, Zhuolun He, Tairu Qiu, Haoyuan Wu, Bei Yu
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA. CoRR (2024)
Zhuolun He, Bei Yu
Large Language Models for EDA: Future or Mirage? ISPD (2024)
Yuxuan Zhao, Qi Sun, Zhuolun He, Yang Bai, Bei Yu
AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution. AAAI (2023)
Zhuolun He, Bei Yu
Invited Paper: Heterogeneous Acceleration for Design Rule Checking. ICCAD (2023)
Ziyi Wang, Zhuolun He, Chen Bai, Haoyu Yang, Bei Yu
Efficient Arithmetic Block Identification With Graph Learning and Network-Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA. MLCAD (2023)
Bizhao Shi, Jiaxi Zhang, Zhuolun He, Xuechao Wei, Sicheng Li, Guojie Luo, Hongzhong Zheng, Yuan Xie
Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Wei Zhong, Zhenhua Feng, Zhuolun He, Weimin Wang, Yuzhe Ma, Bei Yu
Efficient Design Rule Checking with GPU Acceleration. DATE (2023)
Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, Bei Yu
AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search. ICCAD (2023)
Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA. CoRR (2023)
Zhuolun He, Yihang Zuo, Jiaxi Jiang, Haisheng Zheng, Yuzhe Ma, Bei Yu
OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration. DAC (2023)
Zhuolun He, Yuzhe Ma, Bei Yu
X-Check: CPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms. ICCAD (2022)
Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, Yu Huang
Functionality matters in netlist representation learning. DAC (2022)
Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, Yibo Lin, Bei Yu
Physical Synthesis for Advanced Neural Network Processors. ASP-DAC (2021)
Zhuolun He, Ziyi Wang, Chen Bail, Haoyu Yang, Bei Yu
Graph Learning-Based Arithmetic Block Identification. ICCAD (2021)
Yuzhe Ma, Zhuolun He, Wei Li, Lu Zhang, Bei Yu
Understanding Graphs in EDA: From Shallow to Deep Learning. ISPD (2020)
Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, Martin D. F. Wong
Learn to Floorplan through Acquisition of Effective Local Search Heuristics. ICCD (2020)
Rui Lin, Ching-Yun Ko, Zhuolun He, Cong Chen, Yuan Cheng, Hao Yu, Graziano Chesi, Ngai Wong
HOTCAKE: Higher Order Tucker Articulated Kernels for Deeper CNN Compression. CoRR (2020)
Ching-Yun Ko, Cong Chen, Zhuolun He, Yuke Zhang, Kim Batselier, Ngai Wong
Deep Model Compression and Inference Speedup of Sum-Product Networks on Tensor Trains. IEEE Trans. Neural Networks Learn. Syst. 31 (7) (2020)
Zhuolun He, Hanxian Huang, Ming Jiang, Yuanchao Bai, Guojie Luo
FPGA-Based Real-Time Super-Resolution System for Ultra High Definition Videos. FCCM (2018)
Zhuolun He, Guojie Luo
FPGA Acceleration for Computational Glass-Free Displays. FPGA (2017)