Low power multi-level-cell resistive memory design with incomplete data mapping.
Dimin NiuQiaosha ZouCong XuYuan XiePublished in: ICCD (2013)
Keyphrases
- low power
- incomplete data
- single chip
- low cost
- power dissipation
- power consumption
- low power consumption
- vlsi architecture
- high speed
- digital signal processing
- high power
- logic circuits
- cmos technology
- missing values
- missing data
- learning bayesian networks
- wireless transmission
- gate array
- mixed signal
- computer vision
- design process
- em algorithm
- bayesian networks
- data sets
- ultra low power