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Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder.
Lei Yang
Hui Liu
C.-J. Richard Shi
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2006)
Keyphrases
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low density parity check
ldpc codes
fpga implementation
decoding algorithm
source code
message passing
error correction
rate allocation
channel coding
hardware implementation
real time
image transmission
channel capacity
distributed video coding
turbo codes
distributed systems
motion estimation