An FPGA implementation of low-density parity-check code decoder with multi-rate capability.
Lei YangManyuan ShenHui LiuC.-J. Richard ShiPublished in: ASP-DAC (2005)
Keyphrases
- low density parity check
- fpga implementation
- ldpc codes
- rate allocation
- error correction
- decoding algorithm
- hardware implementation
- channel capacity
- distributed video coding
- message passing
- channel coding
- unequal error protection
- end to end
- distributed source coding
- error resilience
- image transmission
- error propagation
- low complexity
- rate distortion
- real time
- video transmission
- image processing algorithms
- error resilient
- bitstream
- video coding
- bit rate
- source coding
- transfer function
- bit errors
- source code
- multiscale