Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits.
Lili ZhouCherry WakayamaRobin PandaNuttorn JangkrajarngBo HuC.-J. Richard ShiPublished in: ICCD (2007)
Keyphrases
- integrated circuit
- low density parity check
- bit rate
- distributed video coding
- ldpc codes
- rate distortion
- rate allocation
- bitstream
- video coding
- unequal error protection
- error resilience
- coding efficiency
- video quality
- visual quality
- source coding
- low bit rate
- subband
- image quality
- macroblock
- compression efficiency
- error resilient
- bit plane
- error correction
- rate control
- wyner ziv
- motion vectors
- entropy coding
- inter frame
- channel coding
- decoding algorithm
- coding method
- computational complexity
- bit allocation
- image transmission
- forward error correction
- low complexity
- turbo codes
- error concealment
- video codec
- error propagation
- image sequences
- scalable video coding
- video transmission
- bit errors
- image coder
- compression algorithm
- video compression
- variable length
- motion compensation
- video coding standard
- mode decision
- image coding
- transform domain
- motion estimation
- compressed video
- motion compensated
- coding scheme