A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits.
Lili ZhouCherry WakayamaNuttorn JangkrajarngBo HuC.-J. Richard ShiPublished in: ASP-DAC (2006)
Keyphrases
- low density parity check
- bit rate
- distributed video coding
- rate distortion
- ldpc codes
- bitstream
- video coding
- low power
- rate allocation
- coding efficiency
- visual quality
- error resilience
- unequal error protection
- video quality
- low bit rate
- error resilient
- error correction
- decoding algorithm
- image quality
- rate control
- inter frame
- macroblock
- low cost
- computational complexity
- turbo codes
- wyner ziv
- motion vectors
- data acquisition
- bit plane
- low complexity
- coding method
- video codec
- channel coding
- source coding
- error concealment
- high speed
- video transmission
- motion compensation
- compression algorithm
- entropy coding
- mode decision
- message passing
- end to end
- forward error correction
- high quality
- image transmission
- image coding
- motion estimation
- power consumption
- packet loss
- scalable video
- video signals
- image compression
- wireless channels
- error propagation
- quality assessment
- channel conditions
- motion compensated