Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks.
James AyersKartikeya MayaramTerri S. FiezPublished in: ISCAS (2007)
Keyphrases
- low power
- power consumption
- single chip
- high speed
- low cost
- low power consumption
- cmos technology
- vlsi architecture
- wireless sensor networks
- ultra low power
- logic circuits
- power dissipation
- gate array
- digital signal processing
- mixed signal
- vlsi circuits
- nm technology
- high power
- cmos image sensor
- image sensor
- wireless transmission
- delay insensitive
- power reduction
- analog to digital converter
- digital camera
- energy efficiency
- circuit design
- energy saving
- design process
- energy dissipation
- wireless communication
- embedded systems
- resource constrained