A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS.
Shivam NigamMukund MuraliHari Shanker GuptaSaurabh SaxenaPublished in: VLSID (2023)
Keyphrases
- cmos technology
- phase locked loop
- nm technology
- low power
- power consumption
- low voltage
- high speed
- parallel processing
- power dissipation
- mobile phone
- silicon on insulator
- high voltage
- information and communication technologies
- image sensor
- multipath
- low cost
- floating point
- m learning
- energy consumption
- metal oxide semiconductor