Armin Tajalli

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 39

Top Topics

Root Mean Square

Signal Processing

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Asif Wahid, Rajath Bindiganavile, Armin Tajalli
Hadamard Multi-Tone Signaling in Multi-Wire Pulse Amplitude Modulation for Next Generation Wireline Communication. ISCAS (2024)
Armin Tajalli
Speed-Noise-Power Trade-Offs in Design of Scaled FET Circuits Using $\mathrm{C}/\mathrm{I}_{\mathrm{D}}$ Methodology. LASCAS (2024)
Rajath Bindiganavile, Asif Wahid, Armin Tajalli
A 29 GHz Sub-Sampling PLL with 25.6-fs-rms RJ based on a Discrete-Time Integrating PD in 45nm RF SOI. CICC (2024)
Shea Smith, Armin Tajalli, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang
A Digital Background Calibration Circuit for Coarse-Fine Timing Mismatch in VCO-Based ADCs. IEEE Trans. Circuits Syst. II Express Briefs 71 (8) (2024)
Behdad Jamadi, Shiuh-Hua Wood Chiang, Armin Tajalli
Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. 32 (7) (2024)
Behdad Jamadi, Fariborz T. Ordubadi, Armin Tajalli
Design Flow to Develop Wideband Inverter-Based Circuits Using C/ID Methodology. SMACD (2023)
Alec Adair, Armin Tajalli
Computational Efficiency of Circuit Design and Optimization Algorithms: A Comparative Study. ISCAS (2023)
Shea Smith, Armin Tajalli, Shiuh-Hua Wood Chiang
A VCO Linearization Technique Using Dual-VCO and Interpolation for Time-Based ADCs. MWSCAS (2023)
Sakthidasan Kalidasan, Armin Tajalli
Extending C/ID Methodology for Optimal Implementation of Single-Stage Discrete-Time Amplifiers. SMACD (2023)
Shea Smith, Taylor Barton, Yen-Cheng Kuan, Armin Tajalli, Mau-Chung Frank Chang, Shiuh-Hua Wood Chiang
A 0.12-V 200-Hz-BW 10-Bit ADC Using Quad-Channel VCO and Interpolation Linearization. A-SSCC (2023)
Asif Wahid, Jacob Atkinson, Rajath Bindiganavile, Farzan Jazaeri, Armin Tajalli
-Invariant. IEEE Trans. Circuits Syst. II Express Briefs 70 (7) (2023)
Armin Tajalli, Amin Shokrollahi
Balanced Circuit Topologies and Their Applications in Data Movement. MWSCAS (2022)
Jacob Atkinson, Anthony Bailey, Armin Tajalli
Methodology. IEEE Trans. Very Large Scale Integr. Syst. 30 (10) (2022)
Asif Wahid, Rajath Bindiganavile, Armin Tajalli
Optimal PAM Order for Wireline Communication. ISCAS (2021)
Rajath Bindiganavile, Armin Tajalli
A Controllable KVCO Ring VCO Topology. MWSCAS (2021)
Armin Tajalli
Methodology. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (2) (2021)
Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
Asif Wahid, Sayed Abdullah Sadat, Mostafa Ardakani, Armin Tajalli
Power System Emulator Based on PLL Architecture. ISCAS (2020)
Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli
Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector. VLSI-SoC (Selected Papers) (2020)
Amin Aghighi, Massood Tabib-Azar, Armin Tajalli
An ULP Self-Supplied Brain Interface Circuit. VLSI-SOC (2020)
Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, Kiarash Gharibdoust, Amit Gupta, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh
Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ. CICC (2020)
Amin Aghighi, Armin Tajalli, Mohammad Taherzadeh-Sani
A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors. VLSI-SOC (2020)
Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli
Energy and Area Efficient Mixed-Mode MCMC MIMO Detector. VLSI-SOC (2020)
Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh
A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET. IEEE J. Solid State Circuits 55 (4) (2020)
Asif Wahid, Armin Tajalli
Digitally-Assisted Peak Detector for Periodic Signal. MWSCAS (2020)
Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici
ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links. NEWCAS (2019)
Amin Aghighi, Jacob Atkinson, Nickolas Bybee, Stuart Anderson, Mitchell Crane, Anthony Bailey, Reuben Morell, Ahmed Hassanin, Armin Tajalli
CMOS Amplifier Design Based on Extended $g_{m}/I_{D}$ Methodology. NEWCAS (2019)
Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, John Fox, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, G. Paul, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh
A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET. VLSI Circuits (2019)
Jacob Atkinson, Amin Aghighi, Stuart Anderson, Anthony Bailey, Mitchell Crane, Armin Tajalli
Multi-Stage Current-Steering Amplifier Design Based on Extended gm/ID Methodology. MWSCAS (2019)
Farzan Jazaeri, Arnout Beckers, Armin Tajalli, Jean-Michel Sallese
A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics. MIXDES (2019)
Firat Celik, Ayca Akkaya, Armin Tajalli, Andreas Burg, Yusuf Leblebici
JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS. PRIME (2019)
Rajath Bindiganavile, Armin Tajalli
Spectrum-Efficient Communication Over Copper Using Hybrid Amplitude and Spatial Signaling. MWSCAS (2019)
Ayca Akkaya, Firat Celik, Armin Tajalli, Yusuf Leblebici
A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End. NORCAS (2018)
Gain Kim, Chen Cao, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links. IEEE Trans. Circuits Syst. II Express Briefs (12) (2017)
Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS. NEWCAS (2016)
Kiarash Gharibdoust, Gain Kim, Armin Tajalli, Yusuf Leblebici
A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces. ISCAS (2016)
Gain Kim, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces. IEEE Trans. Circuits Syst. II Express Briefs (12) (2016)
Amin Shokrollahi, Dario Albino Carnelli, John Fox, Klaas L. Hofstra, Brian Holden, Ali Hormati, Peter Hunt, Margaret Johnston, John Keay, Sergio Pesenti, Richard Simpson, David Stauffer, Andrew Stewart, Giuseppe Surace, Armin Tajalli, Omid Talebi Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Fabio Licciardello, Yohann Mogentale, Anant Singh
10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS. ISSCC (2016)
Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects. IEEE J. Solid State Circuits 51 (4) (2016)
Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Alexandre Schmid, Yusuf Leblebici
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Nikola Katic, Ibrahim Kazi, Armin Tajalli, Alexandre Schmid, Yusuf Leblebici
A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces. Int. J. Circuit Theory Appl. 43 (11) (2015)
Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Yusuf Leblebici
Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators. ISCAS (2015)
Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS. ISSCC (2015)
Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces. IEEE J. Solid State Circuits 50 (12) (2015)
Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici
A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS. VLSIC (2015)
Nikola Katic, Ibrahim Kazi, Armin Tajalli, Alexandre Schmid, Yusuf Leblebici
A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces. NORCHIP (2014)
Armin Tajalli, Yusuf Leblebici
Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Armin Tajalli, Yusuf Leblebici
Design trade-offs in ultra-low-power CMOS and STSCL digital systems. ECCTD (2011)
Armin Tajalli, Yusuf Leblebici
Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter. IEEE Trans. Circuits Syst. II Express Briefs (3) (2011)
Armin Tajalli, Yusuf Leblebici
Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2011)
Armin Tajalli, Yusuf Leblebici
Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits. DATE (2010)
Armin Tajalli, Yusuf Leblebici
Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits. J. Low Power Electron. 6 (1) (2010)
Armin Tajalli, Yusuf Leblebici
Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution. ESSCIRC (2010)
Armin Tajalli, Yusuf Leblebici
A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems. ESSCIRC (2010)
Armin Tajalli, Yusuf Leblebici
Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems. ESSCIRC (2009)
Armin Tajalli, Yusuf Leblebici
Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design. ISCAS (2009)
Armin Tajalli, Yusuf Leblebici
Leakage Current Reduction Using Subthreshold Source-Coupled Logic. IEEE Trans. Circuits Syst. II Express Briefs (5) (2009)
Armin Tajalli, Massimo Alioto, Yusuf Leblebici
Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits. IEEE Trans. Circuits Syst. II Express Briefs (2) (2009)
Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici
Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP. Microelectron. J. 40 (6) (2009)
Armin Tajalli, Yusuf Leblebici
A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology. IEEE J. Solid State Circuits 44 (2) (2009)
Armin Tajalli, Yusuf Leblebici
A widely-tunable and ultra-low-power MOSFET-C filter operating in subthreshold. CICC (2009)
Thomas Liechti, Armin Tajalli, Omer Can Akgun, Zeynep Toprak Deniz, Yusuf Leblebici
A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology. APCCAS (2008)
Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. PATMOS (2008)
Pooyan Sakian, Mohsen Saffari, Seyed Mojtaba Atarodi, Armin Tajalli
Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance. IET Circuits Devices Syst. 2 (5) (2008)
Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer
Improving the power-delay product in SCL circuits using source follower output stage. ISCAS (2008)
Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici, Eric A. Vittoz
Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications. IEEE J. Solid State Circuits 43 (7) (2008)
Armin Tajalli, Eric A. Vittoz, Yusuf Leblebici, Elizabeth J. Brauer
Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. ESSCIRC (2007)
Armin Tajalli, Paul Muller, Yusuf Leblebici
Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits. J. Low Power Electron. 3 (3) (2007)
Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit CoRR (2007)
Armin Tajalli, Paul Muller, Yusuf Leblebici
A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication. IEEE J. Solid State Circuits 42 (10) (2007)
Ramin Zanbaghi, Seyed Mojtaba Atarodi, Armin Tajalli
A Power Optimized Base-Band Circuitry for the Low-IF Receivers. ISCAS (2007)
Mohsen Moezzi, Ramin Zanbaghi, Mojtaba Atarodi, Armin Tajalli
A Q-Enhanced Biquadratic Gm-C Filter for High Frequency Applications. ICECS (2006)
Mohsen Saffari, Seyed Mojtaba Atarodi, Armin Tajalli
A 1/4 rate linear phase detector for PLL-based CDR circuits. ISCAS (2006)
Habib Adrang, Reza Lotfi, Khalil Mafinejhad, Armin Tajalli, Saeed Mehrmanesh
A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system. ISCAS (2006)
Saeed Saeedi, Saeid Mehrmanesh, Armin Tajalli, Seyed Mojtaba Atarodi
A technique to suppress tail current flicker noise in CMOS LC VCOs. ISCAS (2006)
Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. ISCAS (2006)
Armin Tajalli, Paul Muller, Mojtaba Atarodi, Yusuf Leblebici
A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology. ESSCIRC (2005)
Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
A fractional delay-locked loop for on chip clock generation applications. ASP-DAC (2005)
Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops. ISCAS (3) (2005)
Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. DATE (2005)
Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi
A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer. ISCAS (5) (2005)
Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici
A low-power, multichannel gated oscillator-based CDR for short-haul applications. ISLPED (2005)
Armin Tajalli, Seyed Mojtaba Atarodi, Abbas Khodaverdi, Farzad Sahandi Esfanjani
Design and optimization of a high PSRR CMOS bandgap voltage reference. ISCAS (1) (2004)
Armin Tajalli, Saeid Mehrmanesh, Seyed Mojtaba Atarodi
A duty cycle control circuit for high speed applications. ISCAS (1) (2004)
Armin Tajalli, Seyed Mojtaba Atarodi
Design considerations for a 1.5-V, 10.7-MHz bandpass gm-C filter in a 0.6µm standard CMOS technology. ISCAS (1) (2003)
Armin Tajalli, Seyed Mojtaba Atarodi
Structured design of an integrated subscriber line interface system and circuit. ISCAS (2) (2003)
Armin Tajalli, Abbas Khodaverdi, Seyed Mojtaba Atarodi
A compact, low power, fully integrated clock frequency doubler. ICECS (2003)
Armin Tajalli, Seyed Mojtaba Atarodi
-C filter structure for low-voltage and high frequency applications. ISCAS (1) (2003)
Mohammad B. Vahidfar, Armin Tajalli, Seyed Mojtaba Atarodi
A low-power subscriber line interface circuit in a high-voltage CMOS technology. ISCAS (5) (2002)
Armin Tajalli, Mojtaba Atarodi, Akbar Adibi
A 1.5-V supply, video range frequency, Gm-C filter. ISCAS (2000)