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A fractional delay-locked loop for on chip clock generation applications.

Pooya TorkzadehArmin TajalliSeyed Mojtaba Atarodi
Published in: ASP-DAC (2005)
Keyphrases
  • high speed
  • power consumption
  • power dissipation
  • low cost
  • data sets
  • analog vlsi
  • low power
  • high density
  • generation process
  • database
  • neural network
  • artificial neural networks
  • single chip
  • critical path
  • vlsi design