A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors.

Amin Aghighi Armin Tajalli Mohammad Taherzadeh-Sani

Published in: VLSI-SOC (2020)

Keyphrases

low power
high speed
cmos technology
power consumption
low cost
nm technology
high power
wireless transmission
single chip
low power consumption
vlsi architecture
vlsi circuits
low voltage
digital signal processing
logic circuits
mixed signal
energy dissipation
gate array