Speed-Noise-Power Trade-Offs in Design of Scaled FET Circuits Using $\mathrm{C}/\mathrm{I}_{\mathrm{D}}$ Methodology.

Published in: LASCAS (2024)

Keyphrases

chip design
trade off
power dissipation
design methodology
high speed
conceptual framework
logic circuits
design process
noisy data
logic synthesis
noise level
low power
noise reduction
real time
power consumption
building blocks
knowledge based systems
denoising
image processing
genetic algorithm