Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits.
Armin TajalliMassimo AliotoYusuf LeblebiciPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2009)
Keyphrases
- power dissipation
- low power
- ultra low power
- power consumption
- high speed
- low cost
- logic circuits
- power reduction
- chip design
- cmos technology
- vlsi circuits
- digital signal processing
- low power consumption
- focal plane
- single chip
- floating gate
- power management
- critical path
- delay insensitive
- high level synthesis
- genetic algorithm