Elizabeth J. Brauer

Publication Activity (10 Years)

Years Active: 1993-2009
Publications (10 Years): 0

Publications

Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici
Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP. Microelectron. J. 40 (6) (2009)
Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. PATMOS (2008)
Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer
Improving the power-delay product in SCL circuits using source follower output stage. ISCAS (2008)
Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici, Eric A. Vittoz
Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications. IEEE J. Solid State Circuits 43 (7) (2008)
Armin Tajalli, Eric A. Vittoz, Yusuf Leblebici, Elizabeth J. Brauer
Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. ESSCIRC (2007)
Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. VLSI-SoC (2006)
Elizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici
Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. ISCAS (2006)
Elizabeth J. Brauer, Yusuf Leblebici
Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic. Circuits, Signals, and Systems (2004)
Elizabeth J. Brauer, Yusuf Leblebici
Low noise MCML prefix adders using 0.18 µm CMOS technology. Circuits, Signals, and Systems (2004)
Elizabeth J. Brauer, Vikram Magoon
Finding efficient inductor geometries in digital CMOS process for RF applications. Circuits, Signals, and Systems (2004)
Elizabeth J. Brauer, James J. Abbas, Brian Callaway, Joshua Colvin, John Farris
Hardware implementation of a neural network pattern shaper algorithm. IJCNN (1999)
Elizabeth J. Brauer, Marek Turowski, James M. McDonough
Additive Decomposition Applied to the Semiconductor Drift-Diffusion Model. VLSI Design 1998 (1) (1998)
Elizabeth J. Brauer, Pradeep Elamanchili
A Full-Swing Bootstrapped BiCMOS Buffer. Great Lakes Symposium on VLSI (1997)
Elizabeth J. Brauer, Ranu Jung, Denise M. Wilson, James J. Abbas
Sensitivity analysis of an analog circuit model of lamprey unit pattern generator. ICNN (1997)
Elizabeth J. Brauer, Ranu Jung, Denise M. Wilson, James J. Abbas
Analog Circuit Model of Lamprey Unit Pattern Generator. Great Lakes Symposium on VLSI (1997)
Elizabeth J. Brauer, Sung-Mo Kang
An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations. ISCAS (1995)
Elizabeth J. Brauer, Sung-Mo Kang
An algorithm for functional verification of digital ECL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (12) (1995)
Elizabeth J. Brauer, Sung-Mo Kang
Estimating Node Voltages in Bipolar Circuits Using Linear Programming. ISCAS (1995)
Elizabeth J. Brauer, Sung-Mo Kang
Functional Verification of ECL Circuits Including Voltage Regulators. ISCAS (1993)