Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP.
Armin TajalliElizabeth J. BrauerYusuf LeblebiciPublished in: Microelectron. J. (2009)
Keyphrases
- ultra low power
- data flow
- logic circuits
- low power
- random access memory
- bit parallel
- logical operations
- modal logic
- low cost
- low voltage
- digital circuits
- automated reasoning
- logic programming
- classical logic
- computational properties
- learning stage
- asynchronous circuits
- probability theory
- proof theory
- inference rules
- pattern matching
- shift register
- high speed
- data sets