Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit.
Paul MullerArmin TajalliSeyed Mojtaba AtarodiYusuf LeblebiciPublished in: DATE (2005)
Keyphrases
- multi channel
- mixed signal
- low power
- vlsi circuits
- high speed
- power consumption
- logic circuits
- power dissipation
- cmos technology
- single channel
- single chip
- gate array
- power reduction
- low cost
- vlsi architecture
- low power consumption
- digital signal processing
- mac protocol
- circuit design
- channel assignment
- image processing
- real time
- digital circuits
- motion estimation
- wireless transmission