Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
Paul MullerArmin TajalliSeyed Mojtaba AtarodiYusuf LeblebiciPublished in: CoRR (2007)
Keyphrases
- multi channel
- mixed signal
- low power
- vlsi circuits
- high speed
- power consumption
- logic circuits
- cmos technology
- power reduction
- power dissipation
- gate array
- single chip
- vlsi architecture
- single channel
- low cost
- nm technology
- digital signal processing
- low power consumption
- channel assignment
- digital circuits
- mac protocol
- real time
- circuit design
- wireless transmission
- energy efficiency