Yi Zhang

Publication Activity (10 Years)

Years Active: 2014-2021
Publications (10 Years): 19

Top Topics

Error Correction

Analog To Digital Converter

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Yanchao Wang, Siladitya Dey, Tao He, Lukang Shi, Jiawei Zheng, Manjunath Kareppagoudr, Yi Zhang, Kazuki Sobue, Koichi Hamashita, Koji Tomioka, Gabor C. Temes
A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW. A-SSCC (2021)
Tao He, Manjunath Kareppagoudr, Yi Zhang, Emanuel Caceres, Un-Ku Moon, Gabor C. Temes
Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2019)
Lukang Shi, Yi Zhang, Yanchao Wang, Manjunath Kareppagoudr, Mahmoud Sadollahi, Gabor C. Temes
A 13b-ENOB Noise Shaping SAR ADC with a Two-Capacitor DAC. MWSCAS (2018)
Yanchao Wang, Lukang Shi, Tao He, Yi Zhang, Chia-Hung Chen, Gabor C. Temes
Robust Continuous-Time MASH Delta Sigma Modulator. MWSCAS (2018)
Tao He, Michael Ashburn, Stacy Ho, Yi Zhang, Gabor C. Temes
A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR. ISSCC (2018)
Tao He, Chia-Hung Chen, Yi Zhang, Gabor C. Temes
Incremental ADC with parallel counting. MWSCAS (2017)
Tao He, Manjunath Kareppagoudr, Un-Ku Moon, Gabor C. Temes, Yi Zhang
Pseudo-pseudo-differential circuits. MWSCAS (2017)
Yi Zhang, Chia-Hung Chen, Tao He, Gabor C. Temes
A 16 b Multi-Step Incremental Analog-to-Digital Converter With Single-Opamp Multi-Slope Extended Counting. IEEE J. Solid State Circuits 52 (4) (2017)
Yi Zhang, Chia-Hung Chen, Tao He, Kazuki Sobue, Koichi Hamashita, Gabor C. Temes
A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW. CICC (2017)
Chia-Hung Chen, Yi Zhang, Tao He, Gabor C. Temes
An incremental analog-to-digital converter with multi-step extended counting for sensor interfaces. ISCAS (2016)
Yi Zhang, Chia-Hung Chen, Tao He, Gabor C. Temes
A 35µW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator. VLSI Circuits (2016)
Chia-Hung Chen, Yi Zhang, Gabor C. Temes
History, present state-of-art and future of incremental ADCs. ESSCIRC (2016)
Xin Meng, Jinzhou Cao, Tao He, Yi Zhang, Gabor C. Temes, Mitsuru Aniya, Kazuki Sobue, Koichi Hamashita
A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays. ESSCIRC (2015)
Chia-Hung Chen, Tao He, Yi Zhang, Gabor C. Temes
Incremental Analog-to-Digital Converters for High-Resolution Energy-Efficient Sensor Interfaces. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (4) (2015)
Yi Zhang, Chia-Hung Chen, Tao He, Gabor C. Temes
A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD Compensation and FIR Feedback. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2015)
Tao He, Yi Zhang, Xin Meng, Gabor C. Temes, Chia-Hung Chen
A 16-bit 1KHz bandwidth micro-power multi-step incremental ADC for multi-channel sensor interface. ISCAS (2015)
Xin Meng, Yi Zhang, Tao He, Pedram Payandehnia, Gabor C. Temes
A noise-coupled time-interleaved delta-sigma modulator with shifted loop delays. ISCAS (2015)
Chia-Hung Chen, Yi Zhang, Tao He, Patrick Yin Chiang, Gabor C. Temes
A Micro-Power Two-Step Incremental Analog-to-Digital Converter. IEEE J. Solid State Circuits 50 (8) (2015)
Xin Meng, Yi Zhang, Tao He, Gabor C. Temes
Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Chia-Hung Chen, Yi Zhang, Tao He, Patrick Yin Chiang, Gabor C. Temes
A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces. CICC (2014)
Xin Meng, Yi Zhang, Tao He, Gabor C. Temes
A noise-coupled low-distortion delta-sigma ADC with shifted loop delays. MWSCAS (2014)
Xin Meng, Tao He, Yi Zhang, Gabor C. Temes
Double-sampled wideband delta-sigma ADCs with shifted loop delays. MWSCAS (2014)
Yi Zhang, Chia-Hung Chen, Tao He, Xin Meng, Gabor C. Temes
A continuous-time ΔΣ modulator with a digital technique for excess loop delay compensation. ISCAS (2014)
Yi Zhang, Chia-Hung Chen, Tao He, Xin Meng, Nancy Qian, Ed Liu, Phillip Elliott, Gabor C. Temes
A 1 V 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback. A-SSCC (2014)