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A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR.

Tao HeMichael AshburnStacy HoYi ZhangGabor C. Temes
Published in: ISSCC (2018)
Keyphrases
  • error correction
  • error detection
  • markov chain
  • data hiding
  • error correcting
  • high speed
  • ldpc codes
  • computational complexity
  • spatial domain
  • channel coding
  • magnetic tape