Ravindranath Naiknaware

Publication Activity (10 Years)

Years Active: 1993-2004
Publications (10 Years): 0

Publications

Ravindranath Naiknaware, Terri S. Fiez
Process-insensitive low-power design of switched-capacitor integrators. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2004)
Ravindranath Naiknaware, Terri S. Fiez
142 dB ΔΣ ADC with a 100 nV LSB in a 3 V CMOS process. CICC (2000)
Ravindranath Naiknaware, Terri S. Fiez
Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations. IEEE J. Solid State Circuits 34 (3) (1999)
Ravindranath Naiknaware, Terri S. Fiez
Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer. ISCAS (2) (1999)
Ravindranath Naiknaware, Terri S. Fiez
Switched-capacitor integrator design optimizing for power and process variations. ISCAS (2) (1999)
Ravindranath Naiknaware, Terri S. Fiez
Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations. IEEE J. Solid State Circuits 34 (3) (1999)
Ravindranath Naiknaware, Terri S. Fiez
Schematic driven module generation for analog circuits with performance optimization and matching considerations. CICC (1998)
Ravindranath Naiknaware, Terri S. Fiez
CMOS analog circuit stack generation with matching constraints. ICCAD (1998)
Ravindranath Naiknaware
Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment. ICCD (1993)
Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa
Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation. ITC (1993)
Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin
Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. VLSI Design (1993)