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Area-efficient pipelining for FPGA-targeted high-level synthesis.

Ritchie ZhaoMingxing TanSteve DaiZhiru Zhang
Published in: DAC (2015)
Keyphrases
  • high level synthesis
  • pattern recognition
  • low cost
  • signal processing
  • high speed
  • parallel architecture
  • artificial intelligence
  • higher order
  • load balancing
  • field programmable gate array
  • real time image processing