Verifying High-Level Latency-Insensitive Designs with Formal Model Checking.
Steve DaiAlicia KlinefelterHaoxing RenRangharajan VenkatesanBen KellerNathaniel Ross PinckneyBrucek KhailanyPublished in: CoRR (2021)
Keyphrases
- model checking
- high level
- formal specification
- formal methods
- temporal logic
- reactive systems
- ctl model update
- finite state
- temporal properties
- formal verification
- model checker
- partial order reduction
- automated verification
- finite state machines
- computation tree logic
- symbolic model checking
- verification method
- process algebra
- transition systems
- epistemic logic
- reachability analysis
- linear temporal logic
- bounded model checking
- programming language
- pspace complete
- specification language
- asynchronous circuits
- abstract interpretation
- alternating time temporal logic
- partial observability