Login / Signup
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis.
Steve Dai
Ritchie Zhao
Gai Liu
Shreesha Srinath
Udit Gupta
Christopher Batten
Zhiru Zhang
Published in:
FPGA (2017)
Keyphrases
</>
high level synthesis
dynamic environments
parallel processing
risk assessment
parallel architecture
artificial intelligence
multi agent
high resolution