High-level Synthesis for Low-power Design.
Zhiru ZhangDeming ChenSteve DaiKeith A. CampbellPublished in: IPSJ Trans. Syst. LSI Des. Methodol. (2015)
Keyphrases
- low power
- high level synthesis
- power consumption
- single chip
- high speed
- low cost
- low power consumption
- vlsi architecture
- gate array
- digital signal processing
- cmos technology
- logic circuits
- power dissipation
- power reduction
- ultra low power
- high power
- design process
- wireless transmission
- pattern recognition
- case study
- real time