A Simulation Based Buffer Sizing Algorithm for Network on Chips.
Anish S. KumarM. Pawan KumarSrinivasan MuraliV. KamakotiLuca BeniniGiovanni De MicheliPublished in: ISVLSI (2011)
Keyphrases
- preprocessing
- computational complexity
- experimental evaluation
- improved algorithm
- high accuracy
- cost function
- matching algorithm
- k means
- learning algorithm
- times faster
- worst case
- np hard
- significant improvement
- objective function
- dynamic programming
- computational cost
- network flow
- high speed
- theoretical analysis
- detection algorithm
- ant colony optimization
- complex networks
- network model
- fully connected
- growing neural gas
- recognition algorithm
- computationally efficient
- probabilistic model
- evolutionary algorithm
- similarity measure