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Rahul Bodduna
ORCID
Publication Activity (10 Years)
Years Active: 2016-2020
Publications (10 Years): 4
Top Topics
Digital Computer
Power Analysis
Countermeasures
Ibm Power Processor
Top Venues
HOST
CoRR
IEEE Comput. Archit. Lett.
VLSI Design
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Publications
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Rahul Bodduna
,
Vinod Ganesan
,
Patanjali SLPSK
,
Kamakoti Veezhinathan
,
Chester Rebeiro
Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER.
IEEE Comput. Archit. Lett.
19 (1) (2020)
Muhammad Arsath K. F
,
Vinod Ganesan
,
Rahul Bodduna
,
Chester Rebeiro
PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance.
HOST
(2020)
Muhammad Arsath K. F
,
Vinod Ganesan
,
Rahul Bodduna
,
Chester Rebeiro
PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance.
CoRR
(2019)
Neel Gala
,
Arjun Menon
,
Rahul Bodduna
,
G. S. Madhusudan
,
V. Kamakoti
SHAKTI Processors: An Open-Source Hardware Initiative.
VLSI Design
(2016)