Greg M. Link

Publication Activity (10 Years)

Years Active: 2003-2009
Publications (10 Years): 0

Publications

Tamer Ragheb, Andrew J. Ricketts, Mosin Mondal, Sami Kirolos, Greg M. Link, Vijaykrishnan Narayanan, Yehia Massoud
Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2009)
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud
Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. ISQED (2007)
Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud
Thermally robust clocking schemes for 3D integrated circuits. DATE (2007)
Konrad Malkowski, Greg M. Link, Padma Raghavan, Mary Jane Irwin
Load Miss Prediction - Exploiting Power Performance Trade-offs. IPDPS (2007)
Greg M. Link, Narayanan Vijaykrishnan
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip CoRR (2007)
Greg M. Link, Narayanan Vijaykrishnan
Thermal Trends in Emerging Technologies. ISQED (2006)
Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. ISQED (2006)
S. Conner, Greg M. Link, S. Tobita, Mary Jane Irwin, Padma Raghavan
Poster reception - Energy/performance modeling for collective communication in 3-D torus cluster networks. SC (2006)
Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. ICCD (2005)
Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. Asia-Pacific Computer Systems Architecture Conference (2005)
Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin
Implementing LDPC Decoding on Network-on-Chip. VLSI Design (2005)
Greg M. Link, Narayanan Vijaykrishnan
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip. DATE (2005)
John Conner, Yuan Xie, Mahmut T. Kandemir, Robert P. Dick, Greg M. Link
FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection. ASP-DAC (2005)
Theocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin
Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip. Adv. Comput. 63 (2005)
Eun Jung Kim, Greg M. Link, Ki Hwan Yum, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Chita R. Das
A Holistic Approach to Designing Energy-Efficient Cluster Interconnects. IEEE Trans. Computers 54 (6) (2005)
Matthew Pirretti, Greg M. Link, Richard R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
Fault Tolerant Algorithms for Network-On-Chip Interconnect. ISVLSI (2004)
Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne H. Wolf
Embedded Hardware Face Detection. VLSI Design (2004)
Theo Theocharides, Greg M. Link, Eric J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit
Evaluating Alternative Implementations for LDPC Decoder Check Node Function. ISVLSI (2004)
Theocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Vamsi Srikantam
A generic reconfigurable neural network architecture as a network on chip. SoCC (2004)
Eun Jung Kim, Ki Hwan Yum, Greg M. Link, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mazin S. Yousif, Chita R. Das
Energy optimization techniques in cluster interconnects. ISLPED (2003)