Sotirios G. Ziavras

ORCID

Publication Activity (10 Years)

Years Active: 1986-2020
Publications (10 Years): 12

Top Venues

UEMCON

ACM Trans. Embed. Comput. Syst.

Microprocess. Microsystems

IET Comput. Digit. Tech.

Publications

William Contreras, Sotirios G. Ziavras
Low-Cost, Efficient Output-Only Infrastructure Damage Detection With Wireless Sensor Networks. IEEE Trans. Syst. Man Cybern. Syst. 50 (3) (2020)
William Contreras, Sotirios G. Ziavras
Efficient infrastructure damage detection and localization using wireless sensor networks, with cluster generation for monitoring damage progression. UEMCON (2017)
William Contreras, Sotirios G. Ziavras
Efficient structural health monitoring with wireless sensor networks using a vibration-based frequency domain pattern matching technique. UEMCON (2017)
Yaojie Lu, Sotirios G. Ziavras
Instruction Fusion for Multiscalar and Many-Core Processors. Int. J. Parallel Program. 45 (1) (2017)
William Contreras, Sotirios G. Ziavras
Wireless sensor network-based pattern matching technique for the circumvention of environmental and stimuli-related variability in structural health monitoring. IET Wirel. Sens. Syst. 6 (1) (2016)
Yaojie Lu, Seyed A. Rooholamin, Sotirios G. Ziavras
Vector Coprocessor Virtualization for Simultaneous Multithreading. ACM Trans. Embed. Comput. Syst. 15 (3) (2016)
Yaojie Lu, Seyed Amin Rooholamin, Sotirios G. Ziavras
Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane Configuration. ISVLSI (2016)
William Contreras, Sotirios G. Ziavras
Wireless sensor network-based infrastructure damage detection constrained by energy consumption. UEMCON (2016)
Seyed A. Rooholamin, Sotirios G. Ziavras
Modular vector processor architecture targeting at data-level parallelism. Microprocess. Microsystems 39 (4-5) (2015)
Spiridon F. Beldianu, Sotirios G. Ziavras
Performance-Energy Optimizations for Shared Vector Accelerators in Multicores. IEEE Trans. Computers 64 (3) (2015)
Khondaker Musfakus Salehin, Roberto Rojas-Cessa, Sotirios G. Ziavras
A Method to Measure Packet Processing Time of Hosts Using High-Speed Transmission Lines. IEEE Syst. J. 9 (4) (2015)
Xiaofang Wang, Sotirios G. Ziavras
A multiprocessor-on-a-programmable-chip reconfigurable system for matrix operations with power-grid case studies. Int. J. Comput. Sci. Eng. 10 (1/2) (2015)
Spiridon F. Beldianu, Sotirios G. Ziavras
ASIC Design of Shared Vector Accelerators for Multicore Processors. SBAC-PAD (2014)
Nitesh B. Guinde, Roberto Rojas-Cessa, Sotirios G. Ziavras
Packet classification using rule caching. IISA (2013)
Spiridon F. Beldianu, Sotirios G. Ziavras
Multicore-based vector coprocessor sharing for performance and energy gains. ACM Trans. Embed. Comput. Syst. 13 (2) (2013)
Spiridon F. Beldianu, Sotirios G. Ziavras
Efficient on-chip vector processing for multicore processors. ISSoC (2013)
Shashank Suresh, Spiridon F. Beldianu, Sotirios G. Ziavras
FPGA and ASIC square root designs for high performance and power efficiency. ASAP (2013)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures. IET Comput. Digit. Tech. 6 (1) (2012)
Ioannis Vlahava, Sotirios G. Ziavras
Message from General Chairs. ICTAI (2012)
Imtiaz Sajid, M. M. Ahmed, Sotirios G. Ziavras
Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm. J. Signal Process. Syst. 67 (2) (2012)
Spiridon F. Beldianu, Christopher Dahlberg, Timothy Steele, Sotirios G. Ziavras
Versatile design of shared vector coprocessors for multicores. Microprocess. Microsystems 36 (7) (2012)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. IEEE Trans. Very Large Scale Integr. Syst. 20 (4) (2012)
Spiridon F. Beldianu, Sotirios G. Ziavras
On-chip Vector Coprocessor Sharing for Multicores. PDP (2011)
Imtiaz Sajid, Sotirios G. Ziavras, M. M. Ahmed
FPGA-based Normalization for Modified Gram-Schmidt Orthogonalization. VISAPP (2) (2010)
Sara Motahari, Sotirios G. Ziavras, Quentin Jones
Online anonymity protection in computer-mediated communication. IEEE Trans. Inf. Forensics Secur. 5 (3) (2010)
Imtiaz Sajid, Sotirios G. Ziavras, M. M. Ahmed
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance. DSD (2010)
Spiridon F. Beldianu, Roberto Rojas-Cessa, Eiji Oki, Sotirios G. Ziavras
Scheduling for input-queued packet switches by a re-configurable parallel match evaluator. IEEE Commun. Lett. 14 (4) (2010)
Nitesh B. Guinde, Sotirios G. Ziavras
Efficient hardware support for pattern matching in network intrusion detection. Comput. Secur. 29 (7) (2010)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array. ISVLSI (2010)
Nitesh B. Guinde, Sotirios G. Ziavras
Novel FPGA-Based Signature Matching for Deep Packet Inspection. WISTP (2010)
Sara Motahari, Sotirios G. Ziavras, Quentin Jones
Designing for different levels of social inference risk. SOUPS (2009)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. IEEE Trans. Computers 58 (9) (2009)
Muhammad Z. Hasan, Sotirios G. Ziavras
Customized kernel execution on reconfigurable hardware for embedded applications. Microprocess. Microsystems 33 (3) (2009)
Sara Motahari, Sotirios G. Ziavras, Quentin Jones
Preventing Unwanted Social Inferences with Classification Tree Analysis. ICTAI (2009)
Spiridon F. Beldianu, Roberto Rojas-Cessa, Eiji Oki, Sotirios G. Ziavras
Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches. ICCCN (2009)
Sara Motahari, Sotirios G. Ziavras, Mor Naaman, Mohamed Ismail, Quentin Jones
Social Inference Risk Modeling in Mobile and Social Applications. CSE (3) (2009)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras, Sung Woo Chung
Exploiting narrow-width values for thermal-aware register file designs. DATE (2009)
Jie S. Hu, Shuai Wang, Sotirios G. Ziavras
On the Exploitation of Narrow-Width Values for Improving Register File Reliability. IEEE Trans. Very Large Scale Integr. Syst. 17 (7) (2009)
Sara Motahari, Sotirios G. Ziavras, Richard P. Schuler, Quentin Jones
Identity Inference as a Privacy Risk in Computer-Mediated Communication. HICSS (2009)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
Self-Adaptive Data Caches for Soft-Error Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (8) (2008)
Dejiang Jin, Sotirios G. Ziavras
Robust scalability analysis and SPM case studies. J. Supercomput. 43 (3) (2008)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
BTB Access Filtering: A Low Energy and High Performance Design. ISVLSI (2008)
Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras
Asymmetrically banked value-aware register files for low-energy and high-performance. Microprocess. Microsystems 32 (3) (2008)
Xin Tang, Constantine N. Manikopoulos, Sotirios G. Ziavras
Generalized Anomaly Detection Model for Windows-based Malicious Program Behavior . Int. J. Netw. Secur. 7 (3) (2008)
Xiaofang Wang, Sotirios G. Ziavras
Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors. ISQED (2007)
Xiaofang Wang, Sotirios G. Ziavras, Jie S. Hu
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors. ERSA (2007)
Dejiang Jin, Sotirios G. Ziavras
A Study of Data Exchange Protocols for the Grid Computing Environment. ICNS (2007)
Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie S. Hu
Vector Processing Support for FPGA-Oriented High Performance Applications. ISVLSI (2007)
Kanchan Devarakonda, Sotirios G. Ziavras, Roberto Rojas-Cessa
Measuring Network Parameters with Hardware Support. ICNS (2007)
Hongyan Yang, Sotirios G. Ziavras, Jie S. Hu
FPGA-based Vector Processing for Matrix Operations. ITNG (2007)
Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras
Asymmetrically Banked Value-Aware Register Files. ISVLSI (2007)
Muhammad Z. Hasan, Sotirios G. Ziavras
Runtime Partial Reconfiguration for Embedded Vector Processors. ITNG (2007)
Sotirios G. Ziavras, Alexandros V. Gerbessiotis, Rohan Bafna
Coprocessor design to support MPI primitives in configurable multiprocessors. Integr. 40 (3) (2007)
Muhammad Z. Hasan, Sotirios G. Ziavras
Resource management for dynamically-challenged reconfigurable systems. ETFA (2007)
Muhammad Z. Hasan, Sotirios G. Ziavras
Partially Reconfigurable Vector Processor for Embedded Applications. J. Comput. 2 (9) (2007)
Hongyan Yang, Sotirios G. Ziavras, Jie S. Hu
Reconfiguration support for vector operations. Int. J. High Perform. Syst. Archit. 1 (2) (2007)
Xizhen Xu, Sotirios G. Ziavras
A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers. IEICE Trans. Inf. Syst. (2) (2006)
Jie S. Hu, Shuai Wang, Sotirios G. Ziavras
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. DSN (2006)
Xiaofang Wang, Sotirios G. Ziavras
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors. ICCD (2006)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. ICSAMOS (2006)
Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras
Optimizing the Thermal Behavior of Subarrayed Data Caches. ICCD (2005)
Xiaofang Wang, Sotirios G. Ziavras
A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip Multiprocessors. FPT (2005)
Xizhen Xu, Sotirios G. Ziavras
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication. ICCD (2005)
Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. Asia-Pacific Computer Systems Architecture Conference (2005)
Muhammad Z. Hasan, Sotirios G. Ziavras
FPGA-Based Vector Processing for Solving Sparse Sets of Equations. FCCM (2005)
Dejiang Jin, Sotirios G. Ziavras
Modeling distributed data representation and its effect on parallel data accesses. J. Parallel Distributed Comput. 65 (10) (2005)
Xizhen Xu, Sotirios G. Ziavras
A hierarchically-controlled SIMD machine for 2D DCT on FPGAs. SoCC (2005)
Roberto Rojas-Cessa, Ziqian Dong, Sotirios G. Ziavras
Load-balanced CICB packet switch with support for long round-trip times. GLOBECOM (2005)
Xizhen Xu, Sotirios G. Ziavras, Tae-Gyu Chang
An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method. EUC (2005)
Hongyan Yang, Sotirios G. Ziavras
FPGA-based vector processor for algebraic equation solvers. SoCC (2005)
Xiaofang Wang, Sotirios G. Ziavras
A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization. IPDPS (2004)
Dejiang Jin, Sotirios G. Ziavras
A Super-Programming Technique for Large Sparse Matrix Multiplication on PC Clusters. IEICE Trans. Inf. Syst. (7) (2004)
Dejiang Jin, Sotirios G. Ziavras
A Super-Programming Approach for Mining Association Rules in Parallel on PC Clusters. IEEE Trans. Parallel Distributed Syst. 15 (9) (2004)
Satchidanand G. Haridas, Sotirios G. Ziavras
FPGA implementation of a Cholesky algorithm for a shared-memory multiprocessor architecture. Parallel Algorithms Appl. 19 (4) (2004)
Xiaofang Wang, Sotirios G. Ziavras
Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines. Concurr. Comput. Pract. Exp. 16 (4) (2004)
Xiaofang Wang, Sotirios G. Ziavras
Performance optimization of an FPGA-based configurable multiprocessor for matrix operations. FPT (2003)
Sotirios G. Ziavras, Qian Wang, Paraskevi Papathanasiou
Viable Architectures for High-Performance Computing. Comput. J. 46 (1) (2003)
Xizhen Xu, Sotirios G. Ziavras
Iterative Methods for Solving Linear Systems of Equations on FPGA-Based Machines. CATA (2003)
Dejiang Jin, Sotirios G. Ziavras
Load Balancing on PC Clusters with the Super-Programming Model. ICPP Workshops (2003)
Sotirios G. Ziavras
Processor design based on dataflow concurrency. Microprocess. Microsystems 27 (4) (2003)
Xiaofang Wang, Sotirios G. Ziavras
Parallel Direct Solution of Linear Equations on FPGA-Based Machines. IPDPS (2003)
Segreen Ingersoll, Sotirios G. Ziavras
Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs). Microprocess. Microsystems 26 (6) (2002)
Taras I. Golota, Sotirios G. Ziavras
A Universal, Dynamically Adaptable and Programmable Network Router for Parallel Computers. VLSI Design 2001 (1) (2001)
Sotirios G. Ziavras
Versatile Processor Design for Efficiency and High Performance. ISPAN (2000)
Sotirios G. Ziavras, Haim Grebel, Anthony T. Chronopoulos, Florent Marcelli
A new-generation parallel computer and its performance evaluation. Future Gener. Comput. Syst. 17 (3) (2000)
Sotirios G. Ziavras, Sanjay Krishnamurthy
Evaluating the communications capabilities of the generalized hypercube interconnection network. Concurr. Pract. Exp. 11 (6) (1999)
Qian Wang, Sotirios G. Ziavras
Network Embedding Techniques for a New Class of Feasible Parallel Architectures. Applied Informatics (1999)
Qian Wang, Sotirios G. Ziavras
Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities. ISPAN (1999)
Sotirios G. Ziavras
Investigation of Various Mesh Architectures With Broadcast Buses for High-Performance Computing. VLSI Design 1999 (1) (1999)
Sotirios G. Ziavras, Qian Wang
Robust interprocessor connections for very-high performance. Robust Communication Networks: Interconnection and Survivability (1998)
Xi Li, Sotirios G. Ziavras, Constantine N. Manikopoulos
Parallel generation of adaptive multiresolution structures for image processing. Concurr. Pract. Exp. 9 (4) (1997)
Xi Li, Sotirios G. Ziavras, Constantine N. Manikopoulos
Parallel DSP algorithms on TurboNet: an experimental system with hybrid message-passing/shared-memory architecture. Concurr. Pract. Exp. 8 (5) (1996)
Sotirios G. Ziavras
Performance Analysis for an Important Class of Parallel-Processing Networks. ISPAN (1996)
Sotirios G. Ziavras, Arup Mukherjee
Data Broadcasting and Reduction, Prefix Computation, and Sorting on Reduces Hypercube Parallel Computer. Parallel Comput. 22 (4) (1996)
Sotirios G. Ziavras
Scalable Multifolded Hypercubes for versatile Parallel Computers. Parallel Process. Lett. 5 (1995)
Sotirios G. Ziavras, Michalis A. Sideras
Facilitating High-Performance Image Analysis on Reduced Hypercube (RH) Parallel Computers. Int. J. Pattern Recognit. Artif. Intell. 9 (4) (1995)
Sotirios G. Ziavras
Generalized reduced hypercube interconnection networks for massively parallel computers. Interconnection Networks and Mapping and Scheduling Parallel Computations (1994)
Sotirios G. Ziavras
A class of scalable architectures for high-performance, cost-effective parallel computing. SPDP (1994)
Sotirios G. Ziavras, Devenkumar P. Shah
High-performance emulation of hierarchical structures on hypercube supercomputers. Concurr. Pract. Exp. 6 (2) (1994)
Sotirios G. Ziavras
RH: A Versatile Family of Reduced Hypercube Interconnection Networks. IEEE Trans. Parallel Distributed Syst. 5 (11) (1994)

Sotirios G. Ziavras.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Sotirios G. Ziavras