Shuai Wang

Publication Activity (10 Years)

Years Active: 2005-2017
Publications (10 Years): 3

Top Topics

Collaborative Tagging Systems

Vlsi Architecture

Top Venues

IET Comput. Digit. Tech.

Microprocess. Microsystems

Publications

Shuai Wang, Guangshan Duan, Yupeng Li, Qianhao Dong
Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime. ACM Trans. Design Autom. Electr. Syst. 23 (1) (2017)
Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan
Low Power Aging-Aware On-Chip Memory Structure Design by Duty Cycle Balancing. J. Circuits Syst. Comput. 25 (9) (2016)
Shuai Wang, Guangshan Duan
On the characterization and optimization of system-level vulnerability for instruction caches in embedded processors. Microprocess. Microsystems 39 (8) (2015)
Guangshan Duan, Shuai Wang
Exploiting narrow-width values for improving non-volatile cache lifetime. DATE (2014)
Chuanlei Zheng, Shuai Wang
Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors. DFT (2014)
Shuai Wang, Guangshan Duan, Chuanlei Zheng, Tao Jin
Combating NBTI-induced aging in data caches. ACM Great Lakes Symposium on VLSI (2013)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures. IET Comput. Digit. Tech. 6 (1) (2012)
Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan
Low power aging-aware register file design by duty cycle balancing. DATE (2012)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. IEEE Trans. Very Large Scale Integr. Syst. 20 (4) (2012)
Chuanlei Zheng, Parijat Shukla, Shuai Wang, Jie S. Hu
Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors. DFT (2012)
Li Tang, Shuai Wang, Jie S. Hu, Xiaobo Sharon Hu
Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors. ISVLSI (2011)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array. ISVLSI (2010)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors. IEEE Trans. Computers 58 (9) (2009)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras, Sung Woo Chung
Exploiting narrow-width values for thermal-aware register file designs. DATE (2009)
Jie S. Hu, Shuai Wang, Sotirios G. Ziavras
On the Exploitation of Narrow-Width Values for Improving Register File Reliability. IEEE Trans. Very Large Scale Integr. Syst. 17 (7) (2009)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
Self-Adaptive Data Caches for Soft-Error Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (8) (2008)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
BTB Access Filtering: A Low Energy and High Performance Design. ISVLSI (2008)
Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras
Asymmetrically banked value-aware register files for low-energy and high-performance. Microprocess. Microsystems 32 (3) (2008)
Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie S. Hu
Vector Processing Support for FPGA-Oriented High Performance Applications. ISVLSI (2007)
Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras
Asymmetrically Banked Value-Aware Register Files. ISVLSI (2007)
Jie S. Hu, Shuai Wang, Sotirios G. Ziavras
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability. DSN (2006)
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors. ICSAMOS (2006)
Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. Asia-Pacific Computer Systems Architecture Conference (2005)