Low power aging-aware register file design by duty cycle balancing.

Shuai Wang Tao Jin Chuanlei Zheng Guangshan Duan

Published in: DATE (2012)

Keyphrases

low power
single chip
low cost
high speed
power consumption
vlsi architecture
logic circuits
low power consumption
cmos technology
digital signal processing
high power
mixed signal
power dissipation
ultra low power
real time
duty cycle
vlsi circuits
design process
gate array
image processing