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Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors.

Chuanlei ZhengShuai Wang
Published in: DFT (2014)
Keyphrases
  • error rate
  • low cost
  • high speed
  • multithreading
  • parallel implementation
  • real time
  • wireless sensor networks
  • error bounds
  • high density
  • programmable logic