Soft errors issues in low-power caches.
Vijay DegalahalLin LiNarayanan VijaykrishnanMahmut T. KandemirMary Jane IrwinPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2005)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- high power
- wireless transmission
- logic circuits
- vlsi architecture
- single chip
- image sensor
- digital signal processing
- power reduction
- cmos technology
- gate array
- mixed signal
- delay insensitive
- design considerations
- low power consumption
- general purpose
- power dissipation
- ultra low power