Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS.

Matthew Morrison Nagarajan Ranganathan

Published in: VLSI Design (2014)

Keyphrases

power reduction
power consumption
low power
cmos technology
power dissipation
delay insensitive
power saving
high speed
low cost
nm technology
energy efficiency
energy saving
clock gating
digital signal processing
image sensor
data center
real time
computer systems
random access memory