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VLSI architecture and chip for combined invisible robust and fragile watermarking.

Saraju P. MohantyElias KougianosNagarajan Ranganathan
Published in: IET Comput. Digit. Tech. (2007)
Keyphrases
  • vlsi architecture
  • vlsi implementation
  • fragile watermarking
  • low power
  • low cost
  • neural network
  • computer vision
  • frequency domain
  • power consumption