Narender Hanchate

Publication Activity (10 Years)

Years Active: 2004-2022
Publications (10 Years): 1

Top Topics

Machine Learning

Top Venues

Publications

Narender Hanchate
Improving Chip Design Performance and Productivity Using Machine Learning. ISPD (2022)
Narender Hanchate, Nagarajan Ranganathan
Statistical Gate Sizing for Yield Enhancement at Post Layout Level. ISVLSI (2007)
Narender Hanchate, Nagarajan Ranganathan
Integrated Gate and Wire Sizing at Post Layout Level. ISVLSI (2007)
Narender Hanchate, Nagarajan Ranganathan
A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. ACM Trans. Design Autom. Electr. Syst. 11 (3) (2006)
Narender Hanchate, Nagarajan Ranganathan
A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. VLSI Design (2006)
Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate
CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. ISVLSI (2006)
Narender Hanchate, Nagarajan Ranganathan
Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. IEEE Trans. Computers 55 (8) (2006)
Narender Hanchate, Nagarajan Ranganathan
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. ISQED (2006)
Narender Hanchate, Nagarajan Ranganathan
A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. VLSI Design (2004)
Narender Hanchate, Nagarajan Ranganathan
LECTOR: a technique for leakage reduction in CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 12 (2) (2004)