CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL.
Nagarajan RanganathanRavi NamballaNarender HanchatePublished in: ISVLSI (2006)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- nm technology
- single chip
- high power
- wireless transmission
- low power consumption
- vlsi circuits
- cmos technology
- gate array
- power dissipation
- efficient implementation
- evaluation function
- vlsi architecture
- ultra low power
- delay insensitive
- real time
- mixed signal
- power reduction
- image sensor
- hardware implementation
- image compression
- general purpose