LECTOR: a technique for leakage reduction in CMOS circuits.
Narender HanchateNagarajan RanganathanPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2004)
Keyphrases
- delay insensitive
- analog vlsi
- circuit design
- high speed
- vlsi circuits
- low power
- power reduction
- cmos technology
- power consumption
- power dissipation
- floating gate
- chip design
- random access memory
- focal plane
- reduction method
- low cost
- case study
- genetic algorithm
- logic circuits
- low voltage
- image processing
- digital circuits
- computer vision
- data sets