A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors.
Narender HanchateNagarajan RanganathanPublished in: VLSI Design (2004)
Keyphrases
- circuit design
- cmos technology
- floating gate
- low power
- power consumption
- power reduction
- delay insensitive
- high speed
- analog vlsi
- power dissipation
- parallel processing
- low voltage
- flip flops
- mixed signal
- vlsi circuits
- computer controlled
- reduction method
- image processing
- single chip
- signal processing
- chip design
- silicon on insulator