A new approach to minimize leakage power in nano-scale VLSI adder.

Pradeep Jamwal M. B. Srinivas G. V. K. Sarma M. Murali Krishna

Published in: ICWET (2010)

Keyphrases

nano scale
power dissipation
power consumption
chip design
low power
high speed
signal processing
vlsi circuits
image sequences
vlsi design
neural network
logic circuits
gate array
digital signal processing
special case
multi agent
artificial intelligence
genetic algorithm