Chittarsu Raghunandan

Publication Activity (10 Years)

Years Active: 2007-2008
Publications (10 Years): 0

Publications

Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. ISQED (2008)
K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. ISVLSI (2007)
Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas
Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects. ACM Great Lakes Symposium on VLSI (2007)
K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas
Bus encoding schemes for minimizing delay in VLSI interconnects. SBCCI (2007)
Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas
Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN). ISCAS (2007)