A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.
K. S. SainarayananJ. V. R. RavindraM. B. SrinivasPublished in: ISCAS (2006)
Keyphrases
- low power
- high speed
- power dissipation
- cmos technology
- power consumption
- single chip
- vlsi circuits
- deblocking filter
- low cost
- gate array
- vlsi architecture
- coding scheme
- high power
- logic circuits
- digital signal processing
- power reduction
- mixed signal
- wireless transmission
- low power consumption
- real time
- signal processor
- ultra low power
- image sensor
- delay insensitive
- coding method
- coding efficiency