Ashok K. Saxena

Publication Activity (10 Years)

Years Active: 2009-2016
Publications (10 Years): 1

Top Topics

Project Highlights

Digital Computer

Hierarchical Dirichlet Processes

Top Venues

Microelectron. J.

IET Circuits Devices Syst.

J. Circuits Syst. Comput.

Publications

Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET. Microelectron. J. 55 (2016)
Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET. VDAT (2012)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
Dg-FinFET-Based SRAM Configurations for Increased SEU Immunity. J. Circuits Syst. Comput. 21 (4) (2012)
Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta
Impact of dual-k spacer on analog performance of underlap FinFET. Microelectron. J. 43 (11) (2012)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients. IET Circuits Devices Syst. 6 (4) (2012)
Santosh Kumar Vishvakarma, V. Komal Kumar, Ashok K. Saxena, Sudeb Dasgupta
) symmetric double gate MOSFET. Microelectron. J. 42 (5) (2011)
Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta
Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach. SocProS (2) (2011)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact. IET Circuits Devices Syst. 5 (1) (2011)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier. Microelectron. Reliab. 51 (4) (2011)
Balwinder Raj, Jatin Mitra, Deepak Kumar Bihani, V. Rangharajan, Ashok K. Saxena, Sudeb Dasgupta
Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology. J. Low Power Electron. 7 (2) (2011)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation. Microelectron. J. 42 (1) (2011)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
A proposed DG-FinFET based SRAM cell design with RadHard capabilities. Microelectron. Reliab. 50 (8) (2010)
Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta
Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control. J. Low Power Electron. 6 (4) (2010)
Balwinder Raj, Ashok K. Saxena, Sudeb Dasgupta
Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach. EMS (2010)
Y. K. Sudharshan, D. Sreenu, Ashok K. Saxena, Sudeb Dasgupta
Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study. J. Low Power Electron. 5 (1) (2009)