A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design.
Vishal SharmaPranshu BishtAbhishek DalalShailesh Singh ChouhanH. S. JattanaSantosh Kumar VishvakarmaPublished in: VDAT (2018)
Keyphrases
- low power
- single chip
- error correction
- low power consumption
- power consumption
- high speed
- gate array
- low cost
- power reduction
- digital signal processing
- vlsi architecture
- logic circuits
- cmos technology
- error detection
- error correcting
- power saving
- nm technology
- ultra low power
- real time
- image sensor
- embedded systems
- video sequences